The present invention relates to a memory device. In connection with the miniaturization of semiconductor devices, the writing margin and the reading margin of Static Random Access Memory (SRAM) have recently diminished. Some methods to enhance the writing margin have been proposed.
Japanese Laid-open Patent Publication No. 2002-42476 discloses a static semiconductor memory. The static semiconductor memory is provided with a voltage supply circuit. An internal power source line is connected to a memory cell. An external power source line is connected to a power source node and external power source voltage is supplied to the power source node. An internal write-in signal of a H level is inputted to the voltage supply circuit at the time of write-in of data, voltage VCC-VTH is supplied to a memory cell by a N channel MOS transistor. Also, an internal write-in signal of a L level is inputted to the voltage supply circuit at the time of read-out of data, and voltage VCC is supplied to a memory cell by a P channel MOS transistor Japanese Laid-open Patent Publication No. 2007-4960 discloses a semiconductor storage device having a plurality of memory cells arranged in a matrix form, a plurality of cell power supply lines each of which is arranged in association with each of memory cell arrays (columns) and coupled to the memory cells of each corresponding array (column), a plurality of cell power supply lines each of which is arranged in association with each of the memory cell columns and supplies a first power supply voltage to the memory cells of each corresponding column, and a plurality of writing assist circuits each of which is arranged in association with each of the memory cell arrays (columns) and selectively interrupts at least the supply of the first power supply voltage to the corresponding power supply line according to a voltage of the bit lines of the corresponding array (column).
A capacitive write-assist circuit (W-AC) technique described in FIG. 11 is disclosed in “A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with ReadandWrite Cell Stabilizing Circuits” reported in “2006 Symposium on VLSI Circuits”.
The arvdd formed by the 2nd metal layer exists in each column. The downvdd formed by 4th metal layer exists in each of 4 columns. FIG. 12 shows the waveform of read and write cycles. During the read cycle, arvdd=Vdd, and downvdd=GND. During the write cycle, both the arvdd of the selected column and the downvdd are put into a floating state and then the arvdd is shorted to the downvdd by the nMOS. So, the voltage level of arvdd falls in proportion to the capacity ratio between the arvdd node and the downvdd node. In the enlarged drawing of the arvdd waveform of the selected column immediately after starting the write cycle in FIG. 12, the arvdd falls down to 100 mV only 0.3 ns after starting the write cycle.